New Multi-threading Solution From MIPS Technologies Delivers Significant Gains in System Performance for the Embedded Market
February 06 2006 - 8:00AM
PR Newswire (US)
Initial Licensees of the MIPS32(R) 34K(TM) Core Family Include
iVivity, Mobileye and PMC-Sierra MOUNTAIN VIEW, Calif., Feb. 6
/PRNewswire-FirstCall/ -- MIPS Technologies, Inc. (NASDAQ:MIPS),
today introduced the MIPS32(R) 34K(TM) family of cores, a
revolutionary multi-threading solution for high-performance,
cost-sensitive embedded applications. The 34K core family is the
first to implement the MIPS(R) MT ASE and leverages the proven
24KE(TM) microarchitecture that includes the MIPS DSP ASE. With its
multi-threading capabilities, the 34K cores significantly reduce
overall SoC die area, cost, and power consumption. Additionally,
the Company announced early adopter licensees including iVivity,
Mobileye, and PMC-Sierra. Single-threaded microprocessors today
waste many cycles while waiting to access memory, considerably
limiting system performance. The 34K cores are designed to mask the
effect of memory latency by increasing processor utilization. As
one thread stalls, additional threads are instantly fed into the
pipeline and executed, resulting in a significant gain in
application throughput. Internal benchmarks indicate that the
34Kc(TM) core running two threads achieved a 60% speedup over a
single-threaded processor with only a 14% increase in die size.
Additionally, the 34K core family delivers superior real-time
responsiveness for embedded applications. Users can allocate
dedicated processing bandwidth to real-time tasks resulting in a
guaranteed Quality of Service (QoS). This mechanism constantly
monitors the progress of threads and dynamically takes corrective
actions to meet or exceed the real-time requirements. "MIPS
Technologies has taken a straightforward and sensible approach in
implementing multi-threading for embedded applications," said Jim
Turley, principal analyst, Silicon Insider. "It's a well
thought-out strategy that should result in improved system
efficiency and cost savings for MIPS Technologies' new and existing
customers." Usage models The 34K cores can run existing 2-way SMP
operating systems (OSes) and applications with minimal changes. But
it can also be used in environments where independent concurrent
threads have very different roles ("AMP" or asymmetric
multiprocessing). Additionally, the 34K cores can be configured
with a maximum of two VPEs (Virtual Processing Element-a
representation of the OS-only visible state of the MIPS32
architecture) and five TCs (Thread Context-a representation of the
user-state of the MIPS32 architecture) for ultimate design
flexibility. (See figure 1, "MIPS32(R) 34K(TM) Core-Simplified
Overview http://www.newscom.com/cgi-bin/prnh/20060206/SFM083 ).
This dual VPE capability allows the 34K cores to run two
independent operating systems concurrently or alternatively a 2-way
SMP OS. In addition, up to five TCs can be used to allow a single
OS to run up to five processes concurrently. Customers benefit
from: -- Lower system cost -- Improved system performance -- Lower
power consumption -- Additional functionality -- Leveraged software
investment for many applications -- Guaranteed real-time
performance Customer Adoption "The decision to utilize a 34K core
in our storage network processor design came after extensive
internal benchmarking against a competitive multi-core solution,"
said Jim O'Connor, senior vice-president of engineering at iVivity.
"The realized saving in die size and power consumption, coupled
with its compelling performance, made the 34K core stand out as the
clear winner." "Critical to the design of our second generation
Eye-Q2(TM) SoC was application performance, proven reliability and
guaranteed real-time response," said Elchanan Rushinek, vice
president of engineering at Mobileye. "After evaluating competitive
offerings, it was clear the value proposition of the 34K cores'
multi-threading capability was the superior solution." (See
separate release 2/6/06, "Mobileye Licensees MIPS Technologies'
Multi-threading MIPS32(R) 34Kf(TM) Core for Next-Generation Driver
Assistance SoC.") "PMC-Sierra is recognized for our unique ability
to innovate and integrate key technologies in leading-edge SoC
solutions," said Dr. Robert Yung, vice president and chief
technology officer at PMC-Sierra. "The 34K multi-threading
technology offers the superior performance and functionality we
require for some of our next-generation products." "SoC designers
who are serious about tackling the insatiable demand for greater
system performance while addressing the need to reduce system
costs- especially in the consumer market-find the value proposition
of the 34K core family very compelling," said Jack Browne, vice
president of marketing at MIPS Technologies. "We are delighted by
the market's reception to the 34K cores thus far and anticipate
continued rapid adoption." Target Markets and Applications While
the 24K(R) and 24KE core families continue to be MIPS Technologies'
flagship products for single-threaded applications, the new 34K
core family is designed specifically for multi-threaded workloads.
These could be single applications with available explicit threads
such as multiple VoIP channels in home applications. Alternatively,
it could also be used to merge several single-threaded functions
onto a single 34K core -- for example, a host-processor running
Linux and a DSP running an RTOS in an STB application. The
workload-concurrency in network routers and consumer devices such
as Digital TV and DVD recorders means that they, too, benefit from
the 34K cores. The extreme flexibility of the 34K cores enables
them to run in an SMP-like configuration, which makes them an ideal
choice for high-performance imaging devices such as multifunction
printers and scanners. Furthermore, the higher application
throughput combined with the power-efficiency of the 34K cores make
them especially suitable for low-power applications such as digital
cameras, mobile handheld devices and portable media players.
Development Support: The MIPS(R) Ecosystem With MIPS Technologies'
existing third-party vendor relationships and the robust ecosystem
that already supports the MIPS32 architecture, licensees of the 34K
cores can quickly reap the benefits of multi-threading. Key
solution-providers with optimized 34K core support include:
Accelerated Technology now supports the 34K core family with the
Nucleus RTOS and Eclipse-based Nucleus EDGE IDE. The Nucleus RTOS
is robust, scalable and has a minimal memory footprint. The Nucleus
RTOS family of products consists of a complete line of networking,
USB, graphics and file system libraries, providing embedded
developers with everything they need to deploy a wide variety of
embedded applications. The Nucleus EDGE IDE software gives
developers an Eclipse-based development environment. Both of these
products are seamlessly integrated to provide developers with a
comprehensive solution to design and deploy their product to market
quickly and easily. Cadence Encounter(R) Reference Methodology is
available for customers of the 34K core family and provides a fast,
predictable path to high-quality silicon. Cadence Incisive(R)
emulation offers hardware/software co-verification with
Palladium(R), which integrates with FS2 probes and a variety of
software debuggers. CoWare's ConvergenSC provides a powerful,
standards-based environment to develop, analyze, and optimize
SystemC transaction-level platform models, speeding the concurrent
design of SoCs with embedded software at the electronic system
level (ESL). Denali's Databahn(TM) cores provide DDR controller
solutions for high-performance memory sub-systems and facilitate
chip interface design, integration and verification. Coupled with
the multi-threaded capabilities of the 34K cores, their
high-performance memory systems offer customers additional
differentiation in performance, throughput and cost. Express
Logic's ThreadX(R) is a small-footprint, highly efficient RTOS, now
enhanced to support multi-threading on the 34K cores. First Silicon
Solutions (FS2) supports a comprehensive suite of EJTAG debug and
trace tools for the 34K cores. The 34K PDtrace(TM) system, coupled
with the System Navigator(TM) probe, provides best-in-class debug
capabilities including support for hardware based multi-threading,
allowing customers to concurrently capture and view execution flow,
load/store addresses, and the associated data. FS2's tools are
integrated with the GDB/Insight debugger found in the GNU-based
MIPS SDE tool chain, ensuring seamless operation, sophisticated
features, ease of use, and minimal cost to the developer. Green
Hills Software offers a total software development solution that
employs leading-edge compiler technology optimized for the 34K core
family. Magma's reference methodology, based on the Magma Blast
Create(TM) RTL-to-placed gates, Blast Plan(TM) Pro hierarchical
design and the Blast Fusion(R) physical design solutions, enables
the 34K core family to be easily integrated into SoC designs being
implemented with Magma software. Microsoft's next version of
Windows(R) CE will run on the 34K core family. A board support
package (BSP) will be available from the MIPS Technologies'
website. MIPS Technologies' Software Toolkit combines the popular
Free Software Foundation (FSF) Open Source GNU tools with MIPS
Technologies' proprietary runtime libraries that are pre-configured
to many of its popular evaluation boards. The MIPS software
development environment (SDE) supports the latest features of the
34K core family. The MIPS SDE Lite package is available for free
download from http://www.mips.com/. OCP-IP, the industry
association delivering OCP as the standard for IP core interfaces
that facilitate "plug and play" SoC design, defines the
high-performance, out-of-order, on-chip protocol that is employed
in the native interface for all 34K cores. Sonics provides a
scalable intelligent interconnect architecture, boosting 34K-based
system performance and enabling easy integration of other
peripherals. In addition, its SMART Interconnects(TM) allows users
to customize their designs and reduce time to market. Synopsys'
optimized Galaxy(TM) Design Platform reference flow is available
for customers of the 34K core family, helping them meet performance
targets quickly. TimeSys Corporation delivers subscription-based
access to a MIPS32 Linux distribution through LinuxLink by
TimeSys(TM), a commercially-supported Linux solution delivering the
latest Linux features directly from MIPS Technologies. LinuxLink
incorporates an optimized open-source tool chain and enhanced Linux
kernel for the 34K cores, in addition to continuously updated
software components and tools. Virage Logic Corporation's Area,
Speed and Power (ASAP) MemoryT power efficient memory compilers,
and ASAP LogicT standard cell libraries are optimized for MIPS
Technologies' 34K core family. Virtio's VPMM-SC Virtual Platform
for MIPS Malta(TM) development boards models the 34K core family
for software development before hardware availability. This Virtual
Platform offers a choice of instruction-accurate and cycle-accurate
CPU models. VPMM-SC increases a software developer's productivity
by allowing superior visibility and control into the hardware and
software for efficient debug. See http://www.virtio.com/vpmm-sc for
more information. As a leader in the device software optimization
industry, Wind River is excited about the advances that the 34K
core family offers and the innovation it will enable in device
software. Wind River will work with its customers to realize the
benefits of these advances. MIPS32 34Kc Core Product
Specifications(1,2) Process: 90nm G Frequency: 500 MHz (worst case)
Core Size: 2.1 mm2 (core only, extracted from full layout GDSII
database) Power Consumption: 0.56 mW / MHz @ 1.0V (core only) The
MIPS32 34K Core Family The 34K core family includes the 34Kc(TM),
34Kf(TM), 34Kc Pro, and 34Kf Pro cores. 34Kf(TM) Core: Adds
hardware floating point support that is fully compliant with the
IEEE 754 specification. 34K Pro Series(R) Cores: 34Kc Pro and 34Kf
Pro Series cores feature the CorExtend(TM) capability which allows
SoC designers to add proprietary instructions and tightly coupled
hardware. For additional product information please go to
http://www.mips.com/. Availability The 34K core family is generally
available to customers now. About MIPS Technologies MIPS
Technologies, Inc. is a leading provider of industry-standard
processor architectures and cores for digital consumer and business
applications. The company drives the broadest architectural
alliance that is delivering 32- and 64-bit embedded RISC solutions.
The company licenses its intellectual property to semiconductor
companies, ASIC developers and system OEMs. MIPS Technologies and
its licensees offer the widest range of robust, scalable processors
in standard, custom, semi-custom and application-specific products.
The company is based in Mountain View, CA, and can be reached at +1
(650) 567-5000 or http://www.mips.com/. NOTE: MIPS, MIPS32, 24K,
24KE, 34K, 34Kc, 34Kf, Pro Series, Malta and CorExtend are
trademarks or registered trademarks of MIPS Technologies, Inc. in
the US and other countries. All other trademarks referred to herein
are the property of their respective owners. Safe Harbor Statement
by MIPS Technologies, Inc. under the Private Securities Litigation
Reform Act of 1995: Statements made in this news release, other
than statements of historical fact, are forward-looking statements,
including, for example, statements relating to trends, products,
and customer experiences. Forward-looking statements are subject to
a number of known and unknown risks and uncertainties, which might
cause actual results to differ materially from those expressed or
implied by such statements. These risks and uncertainties include
MIPS Technologies' ability to forecast product acceptance and
adoption of technologies by semiconductor companies; to overcome
the challenges associated with establishing licensing relationships
with semiconductor companies; to anticipate business and economic
conditions generally and in the semiconductor industry in
particular; to compete in the market for semiconductor IP
platforms; and other risks. For a further discussion of risk
factors affecting our business, we refer you to the documents we
file from time to time with the Securities and Exchange Commission,
including our Annual Report on Form 10-K for the year ended June
30, 2005 and subsequent Forms 10-Q and 8-K. MIPS Technologies, Inc.
disclaims any intention or duty to update any forward-looking
statements made in this news release. (1) Frequency, power
consumption and size depend upon configuration options, synthesis,
silicon vendor, process, and cell libraries. (2) Configuration: Two
Virtual Processing Elements (VPEs) running four threads, 32K/32K
caches http://www.newscom.com/cgi-bin/prnh/20060206/SFM083
http://photoarchive.ap.org/ DATASOURCE: MIPS Technologies, Inc.
CONTACT: Cathy Browne of MIPS Technologies, Inc., +1-650-567-5178,
or Web site: http://www.mips.com/
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